IBM and Lam Research Announce Collaboration to Advance Sub-1nm Logic Scaling

IBM and Lam Research announced a collaboration aimed at developing new processes and materials to support sub-1nm logic scaling. Building on a long record of successful partnerships, the new agreement will focus on the joint development of novel materials, fabrication processes, and High-NA EUV lithography processes to advance IBM’s logic scaling roadmap.

IBM and Lam have collaborated for more than a decade to advance logic fabrication, notably enabling early generations of 7nm, nanosheet, and EUV process technologies. Under this new five-year agreement, the companies intend to extend logic scaling to the sub-1nm node. The work will focus on developing new materials, advanced etch and deposition capabilities for increasingly complex device architectures, and new High-NA EUV lithography processes to enable next-generation interconnect and device patterning and accelerate industry adoption.

“Lam has been a critical partner to IBM for over a decade, contributing to key breakthroughs in logic scaling and device architecture such as nanosheet and the world’s first 2nm node chip, unveiled by IBM in 2021,” said Mukesh Khare, GM of IBM Semiconductors and VP of Hybrid Cloud, IBM Research. “We are thrilled to be expanding our collaboration to tackle the next set of challenges to enable High-NA EUV lithography and sub-1nm nodes.”

“As the industry enters a new era of 3D scaling, progress depends on rethinking how materials, processes, and lithography come together as a single, high-density system,” said Vahid Vahedi, chief technology and sustainability officer at Lam Research. “We are proud to build on our successful collaboration with IBM to drive High‑NA EUV dry resist and process breakthroughs, accelerating the development of lower power and higher performance transistors that will be critical for AI era.”

Using IBM’s advanced research capabilities at the NY Creates Albany NanoTech Complex and Lam’s end-to-end process tools and innovations, including Aether® dry resist technology, Kiyo® and Akara® etch platforms, Striker® and ALTUS® Halo deposition systems, and advanced packaging technologies — the teams will build and validate full process flows for nanosheet and nanostack devices and backside power delivery. Together, these capabilities are aimed at allowing High‑NA EUV patterns to be reliably transferred into real device layers with high yield and enabling continued scaling, improved performance, and viable paths to production for future logic devices.

Source: IBM and Lam Research media announcement