Antmicro and Google have detailed an open source approach to verification of RISC-V cores that fits with modern software development processes.

The Caliptra project uses the VeeR (Very Efficient & Elegant RISC-V) production grade core hosted by the CHIPS Alliance and based on the SWerV open source cores developed by Western Digital.

Fully reproducible and scalable verification workflows based on open source tooling are especially beneficial for efforts spanning across multiple industrial such as Caliptra, a Root of Trust project driven by Google, AMD, NVIDIA and Microsoft. The project hosts the ongoing development and provide the necessary structure, working environment and support for the reference implementation of a standard originally hosted by Open Compute Project.

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Antmicro and Google worked together on a Continuous Integration (CI) based code quality checks, code indexing, coverage and functional testing pipeline into the RISC-V VeeR core family, discussing the development at this week’s RISC-V Summit Europe in Barcelona. As well as creating a CI development flow, this also uncovered some problems with the hardware design when integrating the core into a system on chip.

VeeR comes in three variants, from the original EH1 – a high-performance single threaded RV32IMCZ core, through a dual-threaded successor, EH2, for IoT and AI systems and down to the EL2 – a tiny and low-power RV32IMC (with partial support for Z extension) core, which is the variant used in the Caliptra project.

The VeeR EL2 core plays a central role in the implementation and, while it is a mature and well-tested technology, keeping both the core itself and its integration with Caliptra consistently tested is important.

Advanced code processing with Verible and Kythe

Many of Antmicro’s efforts focus around building not only the end products but the scalable CI solutions for collaborative hardware development environments that power them. Since Caliptra’s needs for establishing a more open process tie in perfectly with Antmicro’s and all of CHIPS Alliance’s open source-based approach to tooling, we gladly utilized our expertise to help advance VeeR, and by extension, the Caliptra project, in that direction.

One of the core parts of this effort involved Verible, an open source SystemVerilog parser developed by Google in collaboration with Antmicro within CHIPS Alliance, offering a number of code processing functionalities, including linting, formatting, indexing and producing a Kythe schema. Verible comes with a Language Server Protocol which enables integration with popular text editors such as VS Code, Vim, Neovim, Emacs, Sublime, Kakoune and Kate.

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Antmicro’s work with Caliptra involved adding the Verible formatter to the VeeR CI which marks non-compliant formatting changes and uses the reviewdog bot to add comments in the Pull Request Discussion with suggested fixes. A Verible linting Action helps developers maintain good coding practices by providing lint rules for continuous validation of the code, before it even reaches the compilation phase. Notably, the provided lint rules are flexible and can be adjusted based on the project’s requirements, or even turned off completely through creation of a waiver-file or by an inline directive.

Verible’s ability to output a Kythe schema, besides linting and formatting code changes, also provides an indexed overview of the entire codebase, viewable online. The Kythe Verible Indexer, using Verible Indexing Action, enables the user to select multiple repositories to create a set of indexed webpages.

The workflow also checks if a newer revision is available for any of the defined repositories and, if needed, performs indexing. The indexed code browser webpages were deployed for Cores-VeeR-EL2 and Caliptra-rtl.

Using RISCV-dv

The riscv-dv framework is another tool hosted by CHIPS Alliance helping address the complexities of SoC design and verification. It is an SV/UVM based open source instruction generator for RISC-V processors, originally developed for Google’s own needs but currently in use by a wide array of organizations and companies working with verification of RISC-V cores.

The riscv-dv framework generates random instruction chains to exercise certain core features. These instructions are then simultaneously executed by the core (through RTL simulation) and by a reference RISC-V ISS (instruction set simulator), for example Spike or Renode, Antmicro’s open source simulation framework.

Core states of both are then compared after each executed instruction and an error is reported in case of a mismatch.

While working on the Caliptra project, Antmicro introduced the riscv-dv framework for testing the VeeR-EL2 core as well as a GH Actions CI flow which builds or downloads all the dependencies (Verilator, Spike, VeeR-ISS and Renode) and runs the tests. This needed a VeeR-specific execution trace log parser to translate the log to the format understandable by the riscv-dv framework.

CT runners for greater scalability and more flexibility to mix tools

Much like a large part of the industry, the Caliptra project uses Universal Verification Methodology (UVM) as its verification methodology. While Antmicro’s ongoing work on enabling fully open source UVM support in Verilator should ultimately enable completely open source verification, today UVM testbenches or tools like RISC-V DV cannot be run using open source tools only.

Fortunately, this problem already has a solution, also developed within the CHIPS Alliance – custom GitHub Actions Runners that are already in use by a large number of CHIPS projects.

A custom runner setup, currently in development for Caliptra, allows mixing and matching open and closed source tools for CI testing purposes, exposing only the results (such as pass/fail or coverage) with fine-grained control.

Given that RTL design testing and verification of RISC-V based cores and SoCs often require long, memory-consuming and computationally demanding simulations, the custom runners will play another very important role in Caliptra.

While GitHub is the obvious choice for hosting the reference RTL, the processing power and throughput of the CI machines available in GitHub Actions is simply not enough to cover the needs of simulation of complex designs, especially in a highly dynamic, collaborative environment with lots of CI angles.

In order to enable public-facing yet secure CI, and improve the flexibility and scalability of Caliptra’s/VeeR’s pipelines, the custom runners will be deployed for the respective repositories. This setup will enable us to precisely select machines to be used for specific workloads (i.e. the architecture, virtual CPU count, memory size and disk space) but also to use tools stored on an external cloud disk that can be attached to a virtual machine running the job workload.

Seeding other verification methods

The Caliptra SoC is meant as a macro for use in a variety of chip designs, big and small. Various teams adopting Caliptra/VeeR as their Root of Trust solution will need to plug it into a larger ecosystem of tools used in their organization (of course hopefully using Caliptra as a good reference and role model).

On top of the original Caliptra test suite, Antmicro is implementing more specific tests around the VeeR integration in cocotb, a co-simulation testbench library that enables connecting Python coroutines with your HDL simulator of choice. It is currently working on a cocotb testbench that will be able to not only run programs from the generator, but also apply dedicated stimuli and monitor the results in a Python coroutine.

For projects who prefer a more UVM-like testing methodology but need an open source option today, there are also some example tests using pyuvm, a Pythonic library that mirrors the industry accepted SystemVerilog implementation.  A minimal UVM Agent for the programmable interrupt controller of the VeeR-EL2 Core, which will be used to verify handling of the interrupt service routines triggered by external or local-to-core timer interrupts. The verification environment is expected to grow as more test cases could be added, covering the DMA controller, close coupled memory buses or the debug interface.

System level tests use the Open On-Chip Debugger (OpenOCD) and the GNU Project Debugger (GDB). The simulation exposes a virtual JTAG port, which is used to establish a connection with OpenOCD. Then the OpenOCD instance connects to the GNU debugger. Finally, test scripts are run in GDB, which verify core registers content, memory access and peripheral accesses.

This testing methodology exposed an actual problem in the design which prevented accessing system peripherals via JTAG. As it turned out the issue was caused by the side AHB bus of the debug core being disconnected.

Once a connection of the side bus had been made it became possible to access all the peripherals. A 2-to-1 AHB multiplexer was used to join the system and side AHB master ports and forward requests to the peripherals.

Coverage analysis verifies the effectiveness of all kinds of tests, both ISS and RTL level, and help ensure that all design states are properly tested. While open source tools and frameworks have some support for gathering and presenting these metrics as Verilator supports line, toggle and functional coverage, additional work needs to be done to integrate all of those and present them in a comprehensive, visual form, which will be part of our future efforts.

Source: EE News media announcement