Anritsu Strengthens MP1900A BER Test Functions for More Efficient Verification of 400GbE Transceivers and DSP

Multichannel Support, FEC Pattern Generation, ISI, and Error Count Import Functions Reduce Development Time and Speed Time-to-Market

Anritsu Company enhances its Signal Quality Analyzer-R MP1900A BERT with the introduction of four PAM4 BERT options adding multichannel synchronization, multilane FEC pattern generation for 400GbE, Inter Symbol Interference (ISI) stressed signal generation to simulate transmission path losses, and application software for capturing device under test (DUT) error counts. The new options allow engineers to more accurately and efficiently evaluate the bit error rate (BER) of 400GbE transceivers and devices, as well as DSP used by high-speed interfaces in data centers to reduce development time and speed time-to-market. 

The new test functions for the PAM4 pulse pattern generator (PPG) in the MP1900A provide engineers with a single-instrument solution for current standards, as well as emerging technologies. With the options installed, the PPG supports required 400GbE transceiver PHY layer FEC tests, as well as QSFP-DD, and OSFP, making it well-suited to verify newly designed transceivers supporting multilane technologies for PAM4 signal transmissions. It can conduct legacy jitter tolerance and input sensitivity measurements, as well as key tests on the impact of crosstalk due to use of multiple channels and error correction. 

To assure interconnectivity between interfaces defined by the 400GbE standards, the PAM4 PPG now has a built-in function for simulating signals after transmission through a PC board. This new capability, which eliminates the need to prototype multiple PC boards to test transmission path losses, as well as the ISI function allow for more efficient testing.

A built-in function for communicating with the DUT IC error-check function has also been integrated into the MP1900A. The added capability simplifies jitter tolerance measurements during early-stage development of high-speed devices.

The hardware options complement the Error Counts Import function of the MP1900A application software that allows the DUT built-in error-check function measurement results to be displayed on the MP1900A screen. It simplifies IC error measurements and creates a jitter tolerance measurement system for efficient BER tests during IC development. 

The Signal Quality Analyzer-R MP1900A is the market-leading bit error rate tester supporting generation of high-speed signals and signal analysis for 400G and faster speeds. A high-performance BERT with eight slots for modules, such as a 32 Gbit/s Multi-channel PPG/ED, 32G/64G PAM4 PPG, 32G PAM4 ED and Jitter/Noise Generator, the MP1900A supports signal integrity analyses of ever-faster devices. In addition to Physical layer measurement functions for broadband network interfaces, the all-in-one MP1900A supports PCI Express bus and other high-speed interface measurements.

Source: Anritsu Corporation media announcement